library verilog;
use verilog.vl_types.all;
entity XOR32 is
    port(
        XOR32_Input_A   : in     vl_logic_vector(32 downto 1);
        XOR32_Input_B   : in     vl_logic_vector(32 downto 1);
        XOR32_Select    : in     vl_logic;
        XOR32_Output    : out    vl_logic_vector(32 downto 1);
        XOR32_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end XOR32;
